1. Field of the Invention
The present invention relates to methods of identifying semiconductor chip defects on a wafer and classifying those defects based on the type of defect. More particularly, this invention relates to using semiconductor inspection instruments to identify, analyze, and display the number and type of chip defects generated in a wafer.
2. Description of the Related Art
In the field of Defect Review Tools (DRTs), several instruments are widely used to identify and analyze chip defects. For example, Scanning Electron Microscopes (SEMs), made by Hitachi or KLA, and a Focused Ion Beam (FIB), made by FEB, are all widely used for this purpose. In addition to the foregoing instruments, which are used to image defect sources for review, the recent technological trend has been toward developing an instrument for identifying the cause of these defects by determining the composition of the defect. Commercial instruments implementing this trend have been introduced in the market. The goal of this trend is to overcome technological limits expected to be encountered in defect reduction in around the year 2003. This trend is expected to accelerate during upcoming decades.
Unfortunately, even though these newly introduced DRT instruments that analyze defects based on composition have already helped obtain cleanness levels of Class 1, problems have been encountered in identifying chip defect causes based on defect composition. In particular, defect data obtained using these instruments is complicated. Anyone other than a highly trained specialist therefore has difficulty understanding the defect data obtained by the DRT instrument. A mass production implementation of these DRT instruments is therefore impractical without better analysis tools.
Defect management in mass production of semiconductor products is critical because defects are directly related to mass production yields. Presently, defects are classified according to size using instruments such as SEMs or an AIT, and are classified according to type using instruments having a review station, such as an INS3000 made by Leica.
Defect classifications using these tools, however, remain in a primitive state and can include numerous operator errors. These errors impede the recent trend toward miniaturization of semiconductor devices. Additional analysis is therefore required before defects can be eliminated. In addition, even though some analysis is typically performed to help eliminate defects, it is difficult to correctly classify and analyze defects according to type using the prior art classification methods.
Furthermore, despite the amount of information obtained, that information alone is not sufficient to determine the cause of individual defects. In other words, even though statistical classification and management of the defects is possible, using the information obtained, the information regarding individual defects is not sufficient to determine the cause of that defect. Additional analysis is therefore necessary to get the desired information relating to individual defects.
FIG. 4A illustrates a wafer defect map and a scanning electron microscope according to the prior art. The wafer defect map 10 of FIG. 4A was obtained using the KLA SEM 15, graphically represented by a rectangular box. FIG. 4B is a bar graph of defects classified by type according to the prior art. The data in FIG. 4B was analyzed in a conventional instrument having a review station using the defect map of FIG. 4A.
In the conventional defect review process, pictures of the defects are generally taken using an optic or scanning electron microscope. Classification of defects by type is accomplished using the microscope pictures. When the defect problem in the wafer production process is serious, the cause of defects may also be analyzed by determining defect composition. However, the data obtained from the conventional component analysis is difficult to understand and requires careful review by a skilled technician.
The defects generated on a chip have a significant influence on the yield loss and on the inferiority of chip characteristics. It should be noted, however, that even when there are a hundred chips containing defects, the yield loss is generated in only between about 1 to 30 of those chips (i.e., about 1-30% of the chips having defects). The yield loss is not generated in the other 70 to 99 chips. In other words, the yield loss of one semiconductor process can be different from the yield loss of another process, even though the same number of chips with defects are generated in those processes. The yield loss may also differ according to the type of semiconductor device, as well as the size, location, and type of defect.
For example, a DRAM device chip cannot be produced when a defect exists in an area surrounding a memory cell. When the defect exists within the memory cell, however, the chip can still be used to produce a good chip. This is because a laser repairing process can be used to repair the chip using redundancy cells in the same chip. Accordingly, in DRAM devices, the yield loss depends more upon the position of the defects than on the number of defects.
Chip defects are not the only cause of yield loss in a semiconductor product. Defects in manufacturing processes, such as a photolithography process, an etching process, a diffusion process, an ion implanting process, and a thin film deposition process, can also result in chip failure. It is therefore often difficult to clearly identify the influence of chip defects on yield loss.
As described above, the degree of yield loss resulting from chip defects varies depending on the type of device being manufactured and the processes used to produce that device. In addition, the conditions in a semiconductor manufacturing plant, such as the equipment, surroundings, and treatments can also cause defects. Managing yield by managing defects is therefore extremely difficult.
Presently, the technology that uses chip defects to measure yield loss and identify inferior chip characteristics can identify a total number of defects on a wafer, a total number of defect chips, and can classify defects according to defect size and type. After matching these measurements with yield results, this data is analyzed in several ways. For example, a total number of chip defects is compared to the degree of yield loss as well as to the number of particular kinds of chip defects. The total number of chips having defects is also compared to the degree of yield loss and the number of particular kinds of defects in the chips.
Accordingly, only relative measurements of the yield loss are determined. The yield loss and the particular defect ratios are increased when the total number of defects and the total number of defect chips are increased. Because subsequent semiconductor processes can vary the yield loss in the produced semiconductor device, it is difficult to precisely determine at this stage how the defects will influence the ultimate yield loss. It is therefore also impractical to measure absolute values of the yield loss by the defects.
Korean Patent Application No. 1998-29089 discloses methods of measuring the number of chips in the yield loss and the number of defective chips, by type, based on the semiconductor chip defects. The method described in that application, however, can only properly manage and correctly measure the number of chips with defects in a unit process or between unit processes. Information for each of the defects is insufficient to enable the desired analysis and a quick response to the chip defects is therefore difficult.